1. Field of the Invention
This invention relates to the technical field of integrated circuit package, and more specifically, this invention relates to a high density integrated circuit package structure and an integrated circuit with this package structure.
2. Description of Related Art
The integrated circuit is the core of modern technology and the foundation for developments in modern scientific technology. The instruments based on integrated circuits are indispensable to all scientific research. The integrated circuit is also the foundation for modern civilizations and radically changed the way of modern life. It provides intelligent functions in many fields, such as Web of Things, Internet, computer, television, refrigerator, mobile phone, iPad, iPhone, automatic control and the like.
The manufacturing of integrated circuits comprises design, wafer manufacturing, package and testing. While package is a key process among them. Various package forms built upon package technologies are invented to meet the special requirements of various purposes, such as performance, volume, reliability, shape and cost down.
Integrated circuit package comprises: (1) separating an integrated circuit wafer into single chip by polishing and cutting, which guarantee single crystal material with perfect lattice structure; (2) fixing the chip on the lead frame with conductive adhesive or eutectic; (3) connecting the chip to outer leads with micro connecting wires (micron scale); (4) protecting the chip and the wires with polymer or ceramics and forming them into a product with certain shape.
Integrated circuit package can be classified into sealed ceramic package and plastic package. Sealed ceramic package is a technology to assemble package chips and the bounding material surrounding them with vacuum sealing device. Sealed ceramic package is typically applied in high performance levels. Plastic package, on the other hand, assemble the chips with epoxy resin. Chips are not completely separated from their surroundings, and therefore the surrounding air may penetrate the package and impair the quality. However, the plastic package technology has significant development in the application and performance in recent years, which enables auto manufacturing and meets most of the requirements in civil and industry field with low cost.
Existing package forms of integrated circuits include DIP, SOP, SSOP, TSSOP, MSOP, QFP, PLCO, QFN and DFN. The package structures of SOP, SSOP, TSSOP and MSOP are used for most of civil and industry products due to their small volume, better frequency response, lower inner resistance, less material cost, and high auto manufacturing level. They are also easy to auto operate and provide high production efficiency at low cost.
Package forms of integrated circuits have great impacts on the performance, reliability and cost down. As chip manufacturing technology develops from micron scale to nanometer scale, the Moore's law that the performance per unit area of chips is doubled every 18 months gradually become invalid. In the future, high performance cloud computing, Web of Things and mobile network must rely on the breakthrough of the core technologies of IC manufacturing. It will be more and more difficult to provide the IC with higher speed, larger capacity and low power consumption. Therefore, we need more breakthroughs in package forms and package technologies. The present chip manufacturing technologies of IC are of micron scale or even wider scale, and therefore the chip size is generally larger. In order to accommodate chips with larger size, the package structures become much and much larger and consume more and more raw material. A larger area is needed when the integrated circuit is welded onto a PCB, which costs more. In order to meet various sizes of products, various structures are designed like the SOP, SSOP, TSSOP and MSOP. When the smaller chips are packaged in existing package structures, the performance of frequency response, inner resistance, power consumption, thermal consumption and the life time become worse due to their longer pin wires. As chip manufacturing technology develops from micron scale to sub-micron scale, or even nanometer scale (16 nm is ready to be mass-produced), chip sizes are decreased with geometric series. With the meantime, there is also need to reduce power consumption and improve frequency response and package structures.